The present invention relates to a semiconductor device and a semiconductor bonded substrate used for manufacturing the same and, more particularly, to a semiconductor bonded substrate for use in an IPD (Intelligent Power Device) including a power element section and an IC control section for controlling the power element section both of which are mounted within one chip.
As one conventional method of isolating a power element section and an IC control section of an IPD, junction isolation using P and N layers of high impurity concentration is known. Since, however, it is difficult to completely isolate these sections from each other, the junction isolation is not suitable for the IPD in which the power element section requires a high withstanding voltage.
As another method of element isolation, V-shaped trench isolation using a bonded SOI (Silicon on Insulator) wafer is known. The bonded SOI wafer is obtained by bonding the mirror-finished surface of one silicon wafer to that of another silicon wafer on which an oxide film is formed, and a V-shaped trench is formed in the element forming surface of the SOI wafer to such a depth as to reach the oxide film, with the result that the elements are isolated from each other.
In the V-shaped trench isolation, however, the area of the trench occupied on the element forming surface is so large that a chip is increased in area. There is a physical limit to application of the V-shaped trench to the IPD.
In contrast, trench isolation using a bonded SOI wafer has recently been used widely in the IPD.
FIG. 1 illustrates the constitution of a prior art IPD adopting trench isolation using a bonded SOI wafer.
In the IPD, a bonded SOI wafer 104 is obtained by bonding the mirror-finished surface of a supporting substrate 103 constituted of silicon to that of an active-layer substrate 101 constituted of different silicon on which an oxide film 102 is formed, and an isolation trench 105 is formed in the element forming surface of the wafer 104 to such a depth as to reach the oxide film 102.
An IC control section 108 including a CMOS circuit 107 is formed within an element region (dielectric isolation region) 106 completely surrounded with the isolation trench 105 and oxide film 102, and a power element section 111 including a bipolar transistor 110 is formed within another element region 109.
According to the IPD having the above constitution, both a problem wherein the elements cannot be completely isolated when the power element requires a high withstanding voltage in the junction isolation and a problem wherein the area of the chip is increased in the V-shaped trench isolation.
However, the foregoing prior art PID has the following problems.
The active-layer substrate 101 is formed to thickness of about 15 .mu.m in order to heighten the withstanding voltage and, in this case, the bonded SOI wafer 104 is warped greatly. This warp is suppressed by forming an oxide film 121 of about 1 .mu.m in thickness on the non-element forming surface of the wafer 104.
To form the bonded SOI wafer 104, the substrate 101 of 620 .mu.m in thickness is bonded to the substrate 103 and then polished to thickness of 15 .mu.m, thereby forming an element forming surface. For this reason, crystal defects are easy to occur on the element forming surface of the substrate 101, and an element will be formed where the crystal defects occur.
Furthermore, a technique of forming a deep trench in the active-layer substrate 101 of 15 .mu.m in thickness is required in order to form the isolation trench 105, and a processing margin for forming the trench is low.
As described above, the active-layer substrate has to be increased in thickness on its element forming surface, in order to heighten a withstanding voltage. An oxide film is required to prevent the bonded SOI wafer from being warped. Crystal defects are easy to occur on the element forming surface of the active-layer substrate, and a processing margin for forming the isolation trench is low. Since, moreover, the source and drain electrodes (or emitter and collector electrodes) for switching are formed on the same major surface, it is difficult to reduce the area of a chip and improve in current density.